PARAGON is a modeling package that allows a user to automatically generate VHDL-AMS or Virtual Test Bed (VTB) source code from a graphical interface available for Windows and UNIX based systems. The user begins by creating a model interface: model name, connection points, and model parameters with ranges of validity. Next, the user creates a topology of branches which interweave the connection points and various reference nodes in functional schematic package. Equations for each branch are entered in an equation editor. Finally, a SVG-formatted symbol can be generated in the symbol editor.

The PARAGON project is a combination of two research grants from DARPA and the Office of Naval Research that seeks to create a behavioral modeling package. Results from this research will have a significant impact on several aspects of design and test of mixed-signal SoCs. The first benefit is that behavioral models of these mixed systems will possess a greater degree of accuracy and fidelity than those available at present, while existing in a compact form for efficient execution in mixed-signal simulation. This effort lays the groundwork for further advances in modeling with respect to fault modeling and statistical behavioral modeling. This would of course impact mixed-signal test significantly. Behavioral models are the primary mechanism for representing intellectual property (IP). As more and better modeling tools become available, the ability to package IP for subsequent reuse will be greatly enhanced. This, in turn, strongly influences mixed-signal SoC cycle times because ICs of this complexity depend heavily upon reuse. Lastly, the higher fidelity behavioral models that result from this research enable accurate simulation-based analog and mixed-signal synthesis.

A project funded by a NASA Research Award (NRA-99-OSS-05-1347) to NanoPower, Incorporated is concerned with developing a single SOAC solution to replace the current analog board-level electronics. Because of the system requirements for very low noise and for high voltage sensor bias, it is impractical to merely integrate the current analog design onto a single chip using traditional techniques. Thus, a new design is required.