Algorithms and Tools for Automatic Behavioral Model Generation of Mixed-Signal Systems-on-a-Chip

 

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The objective of this project is to research and develop algorithms and tools for the generation of HDL-based behavioral models. This research will mitigate problems faced in mixed-signal System-on-a-Chip (SoC) design: design verification prior to fabrication, mixed-signal test, and synthesis of mixed-signal circuits.

Results from this research will have a significant impact on several aspects of design and test of mixed-signal SoCs. The first benefit is that behavioral models of these mixed systems will possess a greater degree of accuracy and fidelity than those available at present, while existing in a compact form for efficient execution in mixed-signal simulation. This effort lays the groundwork for further advances in modeling with respect to fault modeling and statistical behavioral modeling. This would of course impact mixed-signal test significantly. Behavioral models are the primary mechanism for representing intellectual property (IP). As more and better modeling tools become available, the ability to package IP for subsequent reuse will be greatly enhanced. This, in turn, strongly influences mixed-signal SoC cycle times because ICs of this complexity depend heavily upon reuse. Lastly, the higher fidelity behavioral models that result from this research enable accurate simulation-based analog and mixed-signal synthesis.

 

This project is operated in conjunction with the Dr. Richard Shi and the University of Washington's Mixed Signal CAD Lab.  Click here to visit his laboratory page.

 

 

Downloads

This is the complete abstract for the DARPA funded project in Adobe PDF format.
 
Large poster for the PARAGON project on display in the laboratory.  JPG format (559 KB)
 
Large poster for the Algorithms and Tools groups of the PARAGON project on display in the laboratory.  JPG format (780 KB)
 
Publication submitted to BMAS conference in October 2001.  Discusses the mathematical procedure that allows poles and zeros to be modeled with changes in operating conditions.  A major component of this procedure, known as the root-localization algorithm, identifies when such an approach is applicable, resulting in models that more accurately reflect the distinctive behavior of the circuit.  Adobe PDF format.
 
Publication submitted to ICCD in September 2001.  Determinant Decision Diagram (DDD) is a variant of binary decision diagrams (BDDs) for representing symbolic matrix determinants and cofactors in symbolic circuit analysis.  Inspired by the ideas of Rudell and Drechsler on BDD minimization, we present a lower-bound based sifting algorithm for reordering the DDD vertices to minimize the DDD size.  Our contributions are (1) an adaptation of Rudell's sifting technique for DDD minimization with new rules for determining vertex signs, and (2) tighter lower bounds developed specifically for DDDs.  On a set of DDD examples from symbolic circuit analysis, experimental results have been demonstrated that the proposed lower-bound bases reordering algorithm can effectively reduce DDD sizes.  It has also been demonstrated that sifting with lower bounds uses about 50% less computation compared to sifting without using lower bounds, and sifting with the new lower bounds reduces the computation further by up to 8% compared to sifting with Drechsler's lower bounds for BDDs.  Adobe PDF format.
 
Presentation describing the DAE modeling method and the DDD method.  Includes milestones for each project.  May require slight delay for download.
 
Presentation detailing the symbolic circuit analysis procedure and reordering of DDDs.  Includes results and conclusions.  May require a slight delay for download.
 
Presentation including an introduction to symbolic analysis and DDDs.  Applies DDD procedures to various circuits and displays results and conclusions.  May require a slight delay for download.