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| Behavioral Modeling Group
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| :::: PARAGON |
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NEWS: Paragon technology is currently being commercialized by Lynguent, Inc.
Please visit Lynguent for more information.
PARAGON
is a modeling package that allows
a user to automatically generate model
code in several Hardware Description
Languages (HDLs) from a graphical
interface available for Windows (and
UNIX) based systems. The tool facilitates
creates of an language independent
model file, from which source code
can be created in languages such as
VHDL-AMS, fREEDA,
VTB
(Virtual Test Bed) and others. The
user begins by creating a model interface:
model name, connection points, and
model parameters with ranges of validity.
Next, the user creates a topology
of branches which interweave the connection
points and various reference nodes
in functional schematic package. Equations
for each branch are entered in an
equation editor. Finally, a SVG-formatted
(XML graphics language) symbol can
be generated in the symbol editor.
The result is a package
that is simple enough for a beginning
modeler to use while remaining functional
enough to encompass the scope of analog
systems. PARAGON is a tool that should
aid modelers of all levels of proficiency.
The PARAGON project
is a combination of research grants
from Defence Advanced Research Projects
Agency (DARPA),
the Office of Naval Research (ONR)
and Semiconductor Research Corporation
(SRC).
Click on either of the links below
for abstracts of the specific projects.
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:::::DOWNLOADS
Released
Versions (1.0, 1.1, etc)
| Release
Date |
Version |
Major Features |
Language
Generation |
Language
Import |
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Paragon
1.0 |
Generation
of multi-domain models including
mechanical, electrical, thermal
and optical. Full support for
semiconductor device modeling.
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VHDL-AMS
VTB
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None |
| Dec.
2003 |
Paragon
1.1 (LATEST) |
In-place
Equation Editing
New
Database format utilizing Abstract
Syntax Tree equation formulation
and MathML representation
Model
Importation (MAST)
At
the present time Mast import
is disabled while the UA research
team works with Lynguent and
Synopsys to make this part of
the OpenMast Initiative
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VHDL-AMS
VTB
(2003)
fREEDA
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MAST
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2004 |
Paragon
2.0 |
Digital
support including a mixed-signal
State Machine Editor
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VHDL-AMS
VTB
fREEDA
Verilog-A/AMS
MAST |
MAST
Ascend
Netlist Importer |
Beta Versions:
Released for testing/evaluation
purposes only: NOT supported by
MSCAD lab
> Latest
Beta Versions for Release (Lab
Private)
> Paragon
Beta Testers Webpage (Lab Private)
:::::Models
Paragon
Models:
PARAGON versions come pre-packaged
with many example models for users
to browse, From simple resistors
to semi-conductor and multi-domain
models, these examples strive to
illstrate the power of this graphical
modeling concept.
The Paragon team very much appreciates
any feedback and user created models.
Work is currently being performed
to allow direct submission of models
to the Paragon model library but,
for the time being, please forward
any feedback and model examples
(zipped model directories) to:
paragon_bugs@engr.uark.edu
:::::Developer Resources
Developer's
Area (Lab Private)
About Paragon:
PARAGON uses PyQt, a binding of
the multi platform Qt libraries
to Python, an extraordinarily powerful
and simple scripting language. Paragon
is built upon the following packages,
libraries of which are included
in each built release:
Qt
3.0 or better (http://www.trolltech.com/)
Python 2.2 (http://www.python.org/)
Sip 3.0 (www.riverbankcomputing.co.uk/sip/)
PyQt 3.0 (http://www.riverbankcomputing.co.uk/pyqt/)
Numeric Python 21.0 (hosted at sourceforge.net)
PyQwt (hosted at sourceforge.net)
PyXML (http://pyxml.sourceforge.net/)
Exhaustive
system requirements have not been
compiled, so one may assume that
any system capable of running these
packages should be acceptable. The
minimum tested specifications include
a Pentium II-233 MHz with 128 MB
of RAM, where the program operated
with an acceptable frame rate.
PARAGON
officially supports Windows 2000
and UNIX operating systems. However,
it has been able to execute flawlessly
on Linux, for those who would try.
The Paragon
Team:
(Developer's areas
of expertise):
- Omair Abbasi
(fREEDA)
- Anthony Austin
(Schematic editing, Statemachine
editing)
- Vivek Chaudhary
(Code Generation Lead: Verilog-A,
VHDL-AMS)
- Chandrasekhar
(VTB, VHDL-AMS, MAST generator)
- Matt Francis
(Interfaces Lead: Composer interface,
Schematic editing)
- Pinki Mallick
(VHDL-AMS, MAST importation, MIE)
Architecture
Information:
Design
Guidelines Presentation
Describes the architecture of the
PARAGON project.
Formatting
Guidelines : This page
contains the accepted guidelines
for interface creation within PARAGON.
Development
Tools Utilized:
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| :::::: Ascend: Algorithms and
Tools for Automatic Behavioral Model
Generation of Mixed-Signal Systems-on-a-Chip |
Navigation:
Technical Papers | Presentations
As the complexity and performance
criteria of analog and mixed-signal
systems are steadily increased,
it becomes crucial for the
design engineers to be able
to perform rapid higher-level
simulations achieved by
using behavioral models.
Behavioral models are used
both for top-down design
and for bottom-up verification.
The primary objective is
to develop systematic methods
for automatic generation
of compact behavioral models
from circuit netlists. A
thrust of this project is
to combine the numerical
and symbolic approaches
into a single, more powerful
approach for model generation.
The efforts
are outlined below:
Bottom-up behavioral model
generation and model order
reduction
o Dominant
pole-zero identification
based equation extraction
from circuit netlists
o Determinant-decision-diagram
based symbolic analysis
for behavioral model generation
o Behavioral
modeling tools prototype
o Modeling
tool prototype for HDL code
generation
o Modeling
tool prototype for model
validation and characterization
o Modeling
tool prototype for capturing
atypical behaviors (noise,
thermal)
o Modeling
tool prototype for model
creation and model order
reduction
The project
impacts include
o Automate
model generation
o Enhance
design insight
o Reduce
design time by impacting
design, verification, and
test
The class
of circuits targeted in
this investigation include
building blocks in wireless
communications and base
band analog processing such
as operational amplifiers,
LNAs, power amplifiers,
mixers, and phase-locked
loops. Some of the primary
behavioral characteristics
to be generated include
various circuit transfer
functions such as DC and
AC gains, input and output
impedance. Further, nonlinear
dynamics will be a major
focus of these investigations.
This
project is sponsored by
DARPA.
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Technical Papers |
H. A. Mantooth
and G. G. E. Gielen, “Guest
editorial - Special Issue
on Behavioral Modeling and
Simulation,”
IEEE Trans. On Computer-Aided
Design, pp. 121-123, vol.
22, no. 2, Feb. 2003.
H. A. Mantooth, L. Ren,
X. Huang, Y. Feng and W.
Zheng, “A survey
of bottom-up behavioral
modeling methods for analog
circuits”, IEEE
International Symposium
on Circuits and Systems,
May 25-28, 2003.
X. Huang,
C. Gathercole and H. A.
Mantooth, “Modeling
nonlinear dynamics in analog
circuits via root localization,”
IEEE Trans. on Computer-Aided
Design, accepted for publication,
Jan. 2003.
C.Gathercole
and H. A. Mantooth, “Pole-zero
localization: A behavioral
modeling method,” IEEE
International Workshop on
Behavioral Modeling and
Simulation, pp. 59-65, Oct.
2001.
V. Chaudhary,
M. Francis, X. Huang, H.
A. Mantooth, “PARAGON
– A mixed-signal behavioral
modeling environment,”
IEEE International Conference
on Communications, Circuits
and Systems (ICCCAS'2002),
June 29-30, 2002, Chengdu,
China.
X.
Huang and H.A.Mantooth,
"Event-driven electrothermal
modeling of mixed-signal
circuits", Proceedings,
2000 IEEE/ACM International
Workshop on Behavioral Modeling
and Simulation, pp.10~15,Oct.
2000.
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Presentations on this project
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Presentation
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Presentation
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